The subject matter described herein is concerned with semiconductor devices and methods of fabricating the same, and in particular relates to a semiconductor device and method of fabricating the same suitable for high integration density.
Semiconductor memory devices can be roughly classified into volatile and nonvolatile devices. Volatile memories, including, for example, dynamic random access memories (DRAM) and static random access memories (SRAM), lose their data when power supplies are removed. Nonvolatile memories retain their data even without power supplies applied to them. A flash memory device is one type of nonvolatile memory device. The flash memories are becoming important devices for use as storage media since they are able to electrically write and erase data in addition to the data retention capability independent of powering backup.
Generally, the flash memory devices employ electrically isolated floating gates for storing information. A cell of the flash memory device is able to store a data bit that is logically ‘0’ or ‘1’ according to presence of charges in the floating gate. However, as the charges remain as free charges in the floating gate, all of the charges can be lost when there is a defect or damage on a tunnel oxide film under the floating gate. Thus, it could be required to form the tunnel oxide film to a large thickness under the floating gate. Such a thicker tunnel oxide film may increase an operation voltage of the flash memory device, making it difficult to implement high integration density and hence raising the rate of power consumption. There has been proposed a floating-trap nonvolatile memory device for the purpose of overcoming the drawback of the weak tunnel oxide film. The floating-trap nonvolatile memory device uses a charge-trapping insulation film, which has traps with deep potentials, as an information storage member. By placing charges in the deep potentials of the traps, it offers stability in retaining the charges even when the tunnel oxide film is partially damaged.
Recent advancement of device technologies demands higher integration density in morphological dimensions of semiconductor devices. Along with higher density of semiconductor devices, it is possible to enhance the capacity of data storage and to reduce power consumption thereof.
However, there are also generated various problems by the higher integration density. For instance, field effect transistors used as unit elements of the semiconductor devices would be degraded in the characteristic of punch-through because of narrower distances between their source and drain regions.
Further, a unit cell of the DRAM is required to have larger capacitance in a restrictive region and vertically higher storage electrodes, which makes it difficult to carry out photolithography and/or etching processes due to high step differences.
Additionally, as an electrically writable/erasable nonvolatile memory device is also required to have larger storage capacity, more memory cells nee to be integrated in a given area. However, since there is a limit to the minimum line width defined by the photolithography process, it becomes more difficult to implement such a larger-capacity nonvolatile memory device.
Therefore, advanced technologies for solving the various problems associated with higher integration density of semiconductor devices are being studied.